MIPS Processor
April 2022 - May 2022
Status: Completed
This project is based on the Xilinx Zynq-7000 System-on-Chip (SoC) in order to design a reduced instruction set MIPS processor. It features a modified MIPS assembly instruction set and compiler in order to run programs, which can be loaded onto the FPGA and executed.
Purpose of the project
After learning the MIPS architecture as part of the Digital Design and Computer Organization, I thought an interesting final project for the class would be to make a reduced instruction set MIPS processor. I decided to do this project since it would offer me a wide knowledge of exactly how MIPS computers operate as well as provide insight into other computer architectures.
Outcome
After completion of this project, I have now proficiency in:
Processor Architecture, Constraints, FPGA Design Methodology
Memory interfacing
Verilog and VHDL
Assembly and C coding for processors
FPGA development workflow
The project ended up as well as I hoped, if not better. I was able to design a reduced instruction set processor which can be used to do a variety of arithmetic functions. In the future, I may decide to expand to a full instruction set MIPS processor, or perhaps switch architectures all together in order to learn other computer designs.
Steps
Design Architecture
The first step is to decide how the computer should be organized. Firstly, I looked at how a standard MIPS processor is organized, and then took some creative freedoms in order to simplify it for this project. By reducing the amount of registers and the amount of bits, I could reduce the necessary storage sizes by a large amount while also maintaining a large amount of functionality. After many iterations, I landed on a design which met all of the project goals.
Code and Test FPGA
Next, the architecture was coded in Verilog to create the desired behavior. First, an ALU and register file module were created, then the necessary IP for memory were created and connected together in the top module. Lastly, the multiplexers needed and instruction decoder module were created. After testing each module thoroughly using custom testbenches written in Verilog, the different modules were combined in order to create a functioning processor that can be programmed using VIO.
Create Assembly Compiler
Lastly, since the processor has a reduced instruction set, I needed to create a compiler so I could create programs for the processor in MIPS assembly. After creating the compiler in C, it was tested with a multiplication program written in MIPS assembly. Although only four registers is definitely limiting, especially compared to a real processor, it was a fun challenge to code different programs such as multiplication with storage constraints.